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Philips Semiconductors FAST Products
Product specification
9-Bit address/data Futurebus transceiver, ADT
74F8965/74F8966
FEATURES
* 9-bit transceiver (both directions) * Drives heavily loaded backplanes with
equivalent load impedances down to 10 ohms * High drive (100mA) open collector drivers on B port * Reduced voltage swing (1V to 2V) produces less noise and reduces power consumption * High speed operation enhances performance of backplane buses and facilitates incident wave switching * Compatible with IEEE 896 futurebus standards and IEEE 1194 BTL standard * Built-in precision band-gap reference provides accurate receiver thresholds and improved noise immunity * Controlled output ramp and multiple GND pins minimize ground bounce * Glitch-free power up/power down operation
TYPE 74F8965 74F8966
* Guaranteed skew of less than 2ns
DESCRIPTION
The 74F8965 and 74F8966 are 9-bit bidirectional latchable transceivers and are intended to provide the electrical interface to a high performance wired-OR bus. The B port inverting drivers are low-capacitance open collector with controlled ramp and are designed to sink 100mA from 2 volts. The B port inverting receivers have a precision band gap references for improved noise margins. The B port interfaces to 'Backplane Transceiver Logic' (BTL). BTL features a reduced (1V to 2V) voltage swing for lower power consumption and a series diode on the drivers to reduce capacitive loading. Incident wave switching is employed, therefore BTL propagation delays are short. Although the voltage swing is much less for BTL, so is its receiver threshold region, therefore noise margins are excellent.
BTL offers low power consumption, low ground bounce, EMI and crosstalk, low capacitive loading, superior noise margin and low propagation delays. This results in a high bandwidth, reliable backplane. The 74F8965 and 74F8966 A ports have TTL 3-state drivers and TTL receivers. The B ports have standard BTL I/O with 100mA current sink capability. The B-to-A path is a simple inverted buffered path. When going from A-to-B the user may choose between a buffered path or a latching function. The 74F8966 also has an idle arbitrator/multiple competitors output. The IAMC output compares, using a wired-OR configuration, the data on the bus to the latched data presented to the bus. If the bus data matches the data presented by the 74F8966 then IAMC is high. If the data doesn't match then IAMC goes low.
TYPICAL PROPAGATION DELAY 3.5ns 3.5ns
TYPICAL SUPPLY CURRENT( TOTAL) 80mA 80mA
ORDERING INFORMATION
DESCRIPTION 44-pin PLCC ORDER CODE COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C N74F8965A, N74F8966A
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS A0 - A8 B0 - B8 OEA, OEB0, OEB1 LS IAREQ LE A0 - A8 B0 - B8 IAMC TTL data inputs Data inputs with threshold circuitry Output enable inputs Latch select (active low) ('F8965) Idle arbitration request (active low) ('F8965) Latch enable input (active low) 3-state TTL outputs Open collector BTL outputs Idle arbitration/multiple competitors output ('F8966) DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/0.033 5.0/0.167 1.0/0.167 1.0/0.167 1.0/0.167 1.0/0.167 150/40 OC/166.7 OC/80 LOAD VALUE HIGH/LOW 20A/20A 100A/100A 20A/100A 20A/100A 20A/100A 20A/100A 3mA/24mA OC/100mA OC/48mA
Notes to input and output loading and fan out table 1. One (1.0) FAST unit load is defined as: 20A in the high state and 0.6mA in the low state. 2. OC = Open collector.
December 19, 1990
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853 1526 01320
Philips Semiconductors FAST Products
Product specification
9-Bit address/data Futurebus transceiver, ADT
74F8965/74F8966
PIN CONFIGURATION PLCC
LOGIC BUS BUS LOGIC A1 GND A0 VCC OEA OEB0 OEB1 VCC GND 6 LOGIC GND A2 LOGIC GND 7 8 9 5 4 3 2 1 44 43 42
IEC/IEEE SYMBOL
74F8965 74F8965
B0 41 BUS GND 40 23 39 B1 38 BUS GND 37 B2 36 BUS GND 35 B3 34 BUS GND 33 B4 32 BUS GND 31 B5 30 BUS GND 29 B6 6 8 1 44 22 2 4 4D 1 G1/V2 & 2 C4 EN5 1 1 MUX 1 3 39 37 35 33 31 29 27 25 41 EN3
A3 10 LOGIC GND 11 A4 12 A5 13 LOGIC GND 14 A6 15 LOGIC GND 16 A7 17 18 19 20 21 22 23 LS 24 BUS VCC 25 B8 26 27 28 BUS GND
10 12 13 15 17 19
LOGIC A8 LOGIC LOGIC LE GND GND V CC
BUS B7 GND
PIN CONFIGURATION PLCC
74F8966
BUS BUS LOGIC LOGIC A1 GND A0 VCC OEA OEB0 OEB1 VCC GND 6 LOGIC GND A2 LOGIC GND 7 8 9 5 4 3 2 1 44 43 42 B0 41 BUS GND 40 39 B1 38 BUS GND 37 B2 36 BUS GND
IEC/IEEE SYMBOL
74F8966
23 1 44 22 2
10 11 G1/V2/EN6 12 13 & EN3 14 15 2 16 C4 17 18 EN5 1
1
20
A3 10 LOGIC GND 11 A4 12 A5 13 LOGIC GND 14 A6 15 LOGIC GND 16 A7 17 18 19 20 21 22 23 24 25 B8 26 27 28 BUS GND
41 7 Z10
4 35 B3 34 BUS GND 33 B4 32 BUS GND 31 B5 30 BUS GND 29 B6 6 8 10 12 13 15 17 19 4D
1 1 N7 1
MUX 3 39 37 35 33 31 29 27 25
LOGIC A8 GND
IAMC LOGIC LE IREQ BUS VCC VCC
BUS B7 GND
December 19, 1990
2
Philips Semiconductors FAST Products
Product specification
9-Bit address/data Futurebus transceiver, ADT
74F8965/74F8966
LOGIC SYMBOL
74F8965
4 6 8 10 12 13 15 17 19 4 6 8
74F8966
10 12 13 15 17 19
A0 A1 A2 A3 A4 A5 A6 A7 A8 1 44 23 22 2 OEB0 OEB1 LS LE OEA B0 B1 B2 B3 B4 B5 B6 B7 B8 1 44 23 22 2 20 OEB0 OEB1 IAREQ LE OEA IAMC
A0 A1 A2 A3 A4 A5 A6 A7 A8
B0 B1 B2 B3 B4 B5 B6 B7 B8
41 39 37 35 33 31 29 27 25 41 39 37 35 33 31 29 27 25 Logic VCC = Pin 3, 21 Logic GND = Pin 5, 7, 9, 11, 14, 16, 18
Logic VCC = Pin 3, 21 Logic GND = Pin 5, 7, 9, 11, 14, 16, 18, 20
PIN DESCRIPTION
SYMBOL A0 - A8 B0 - B8 OEB0 OEB1 OEA LE LS IAREQ IAMC Bus GND Logic GND Bus VCC Logic VCC PINS 4, 6, 8, 10, 12, 13, 15, 17, 19 41, 39, 37, 35, 33, 31, 29, 27, 25 1 44 2 22 23 23 20 26, 28, 30, 32, 34, 36, 38, 40, 42 5, 7, 9, 11, 14, 16, 18, 20 (74F8965) 24, 43 3, 21 TYPE I/O I/O Input Input Input Input Input Input Output Ground Ground Power Power NAME AND FUNCTION Data inputs/TTL 3-state outputs Data inputs / open collector outputs, high current drives. Output enable input. Enables the B outputs when high. Output enable input. Enables the B outputs when low. Output enable input. Enables the A outputs when high. Latch enable input. Enables latch when low. Latch select input. Selects latch when low (74F8965). Idle arbitration request input (74F8966). Idle arbitration/multiple competitors output (open collector output) (74F8966). Bus ground (0V) Logic ground (0V) Positive supply voltages Positive supply voltages
December 19, 1990
3
Philips Semiconductors FAST Products
Product specification
9-Bit address/data Futurebus transceiver, ADT
74F8965/74F8966
LOGIC DIAGRAM FOR 74F8965
OEB0 OEB1
1 44
LS LE OEA
23 22 2 DQ E 41 B0
A0
4
DQ E A1 6 39 B1
DQ E A2 8 DQ E A3 10 35 B3 37 B2
DQ E 33 B4
TTL levels
A4
12
BTL levels
DQ E A5 13 31 B5
DQ E A6 15 29 B6
DQ E A7 17 27 B7
DQ E A8 19 25 B8
Logic VCC = Pin 3, 21 Logic GND = Pin 5, 7, 9, 11, 14, 16, 18, 20
December 19, 1990
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Philips Semiconductors FAST Products
Product specification
9-Bit address/data Futurebus transceiver, ADT
74F8965/74F8966
LOGIC DIAGRAM FOR 74F8966
OEB0 OEB1 1 44 48mA open collector
IAREQ LE OEA
23 22 2 DQ E 4
20
IAMC
TTL level
41
B0
A0
DQ 6 A1 E 39 B1
DQ 8 A2 E 37 B2
DQ 10 A3 E 35 B3
DQ
TTL levels
12 A4
E
33
B4
BTL levels
DQ 13 A5 E 31 B5
DQ 15 A6 E 29 B6
DQ 17 A7 E 27 B7
DQ 19 A8 Logic VCC = Pin 3, 21 Logic GND = Pin 5, 7, 9, 11, 14, 16, 18 E 25 B8
December 19, 1990
5
Philips Semiconductors FAST Products
Product specification
9-Bit address/data Futurebus transceiver, ADT
74F8965/74F8966
FUNCTION TABLE FOR 74F8965
INPUTS AIn L H L H l h - - X X X - - - Bn* - - - - - - - - - X X L H X OEB0 H H H H H H H H H L X L L X OEB1 L L L L L L L L L X H H H X LS H H L L L L L L L X H H H X OEA L L L L L L H H L X X H H L LE X X L L H H H X X X X X LATCH STATE X X H L H L H L NC X X X X X OUTPUTS An input input input input input input L H input X X H L Z Bn H** L H** L H** L H** L L H** H** input input X Disable An outputs Bn to An An to Bn outputs latched and read (preconditioned latch) An to Bn hold Disable Bn outputs An to Bn latch and read An to Bn transparent latch An to Bn bypass latch OPERATING MODE
Notes to function table for 74F8965 1. H = High voltage level 2. h = High voltage level one setup time prior to the low-to-high LE transition 3. L = Low voltage level 4. l = Low voltage level one setup time prior to the low-to-high LE transition 5. NC= No change 6. X = Don't care 7. Z = High impedance "off' state 8. - = Input not externally driven 9. = Low-to-high transition 10.H**= Goes to level of pullup voltage. 11. B* = Precaution should be taken to insure B inputs do not float. If they do they are equal to low state.
FUNCTION TABLE FOR 74F8966
INPUTS AIn L H L H l h - - X X X - - - - - Bn* - - - - - - - - - X X L H Bn Bn X OEB0 H H H H H H H H H L X L L L L X OEB1 L L L L L L L L L X H H H H H X IAREQ L L L L L L L L L X H H H H H X LS H H L L L L L L L X H H H * * X OEA L L L L L L H H L X X H H H H L LE X X L L H H H X X X X H H X LATCH STATE X X H L H L H L NC X X X X Bn Bn X An input input input input input input L H input X X H L Z Z Z OUTPUTS Bn H** L H** L H** L H** L NC H** H** input input Bn Bn X IAMC H** H** H** H** H** H** H** H** H** H** H** H** H** L H** X Latch Bn data idle arbitration request (preconditioned latch) Disable An outputs Bn to An An to Bn outputs latched and read (preconditioned latch) An to Bn hold Disable Bn outputs An to Bn latch and read An to Bn transparent latch An to Bn bypass latch OPERATING MODE
December 19, 1990
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Philips Semiconductors FAST Products
Product specification
9-Bit address/data Futurebus transceiver, ADT
74F8965/74F8966
Notes to function table for 74F8966 1. H = High voltage level 2. h = High voltage level one setup time prior to the low-to-high LE transition 3. L = Low voltage level 4. l = Low voltage level one setup time prior to the low-to-high LE transition 5. NC= No change 6. X = Don't care 7. Z = High impedance "off' state 8. - = Input not externally driven 9. = Low-to-high transition 10.* = High-to-low transition, latch must be preconditioned before IAREQ 11. H**= Goes to level of pullup voltage. 12.B* = Precaution should be taken to insure B inputs do not float. If they do they are equal to low state.
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) SYMBOL VCC VIN Supply voltage Input voltage OEB0, OEB1, LEA, LE A0 - A8, B0 - B8 IIN VOUT Input current Voltage applied to output in high output state A0 - A8 IOUT Current applied to output in low output state Operating free air temperature range Storage temperature range IAMC (74F8966 only) B0 - B8 PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -0.5 to +5.5 -40 to +5 -0.5 to VCC 48 96 200 0 to +70 -65 to +150 UNIT V V V mA V mA mA mA
Tamb Tstg
C C
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VIH Supply voltage High-level input voltage Except B0 - B8 B0 - B8 VIL Low-level input voltage Except B0 - B8 B0 - B8 IIk IOH VOH Input clamp current High-level output current High-level output voltage A0 - A8 IAMC (74F8966 only) A0 - A8 IOL Low-level output current IAMC (74F8966 only) B0 - B8 Tamb Operating free air temperature range 0 4.5 24 48 100 +70 PARAMETER MIN 4.5 2.0 1.625 1.55 0.8 1.475 -18 -3 NOM 5.0 MAX 5.5 UNIT V V V V V mA mA V mA mA mA
C
December 19, 1990
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Philips Semiconductors FAST Products
Product specification
9-Bit address/data Futurebus transceiver, ADT
74F8965/74F8966
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL IOH IOFF VOH VOL VIK II PARAMETER High-level output current B0 - B8 IAMC (74F8966) Power-off output current B0 - B8 IAMC (74F8966) High-level output voltage A0 - A84 A0 - A84 Low-level output voltage IAMC (74F8966) B0 - B8 Input clamp voltage Input current at maximum input voltage OEB0, OEB1, OEA, LE, LS, IAREQ A0 - A8, B0 - B8 OEB0, OEB1, OEA, LE, LS, IAREQ B0 - B8 OEB0, OEB1, OEA, LE, LS, IAREQ B0 - B8 IIH + IOZH IIL + IOZL IOS Off-state output current, high-level voltage applied Off-state output current, low-level voltage applied Short circuit output current3 A0 - A8 only AO8 ICCH ICCL ICCZ A0 - A8 TEST CONDITIONS1 VCC = MAX, VIL = MAX, VIH = MIN, VOH = 2.1V VCC = MAX, VIL = MAX, VIH = MIN, VOH = 4.5V VCC = 0.0V, VIL = MAX, VIH = MIN, VOH = 2.1V VCC = 0.0V, VIL = MAX, VIH = MIN, VOH = 4.5V VCC = MAX, VIL = MAX, VIH = MIN, IOH = -3mA VCC = MIN, VIL = MAX VIH = MIN VCC = MIN, II = IIK VCC = MAX, VI = 7.0V IOL = 24mA IOL = 48mA IOL = 100mA 0.75 1.0 2.4 MIN LIMITS TYP2 MAX 100 100 100 100 VCC 0.50 0.50 1.10 -1.2 100 A A A A V V V V V A UNIT
VCC = MAX, VI = 5.5V VCC = MAX, VI = 2.7V VCC = MAX, VI = 2.1V VCC = MAX, VI = 0.5V VCC = MAX, VI = 0.3V VCC = MAX, VO = 2.7V VCC = MAX, VI = 0.5V VCC = MAX VCC = MAX VCC = MAX, VIL = 0.5V -60 80 85 75
1 20 100 -100 -100 50 -50 -150 140 145 100
mA A A A A A A mA mA mA mA
IIH
High-level input current
IIL
Low-level input current
ICC
Supply current (total)
Notes to DC electrical characteristics 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 4. Due to test equipment limitations, actual test conditions are for VIH =1.8V and VIL = 1.3V.
December 19, 1990
8
Philips Semiconductors FAST Products
Product specification
9-Bit address/data Futurebus transceiver, ADT
74F8965/74F8966
AC ELECTRICAL CHARACTERISTICS
A PORT LIMITS Tamb = +25C SYMBOL PARAMETER TEST CONDITION VCC = +5.0V CL = 50pF, RL = 500 MIN tPLH tPHL tPZH tPZL tPHZ tPLZ tsk(o) Propagation delay Bn to An Output enable time to high or low, OEA to An Output disable from high or low, OEA to An Skew between receivers in same package Waveform 2 Waveform 5, 6 Waveform 5, 6 Waveform 4 3.0 2.5 7.5 9.0 3.0 4.0 TYP 5.0 4.5 9.0 11.0 5.0 6.0 0.5 Tamb = +25C SYMBOL PARAMETER TEST CONDITION VCC = +5.0V CD = 30pF, RU = 9 MIN tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tsk(o) Propagation delay An to Bn (transparent latch) Propagation delay An to Bn (bypass latch) Propagation delay LE to Bn Output enable/disable time, OEB0 to Bn Output enable/disable time, OEB1 to Bn Propagation delay IAREQ or LS to Bn Transition time, Bn port 10% to 90%, 90% to 10% Skew between drivers in same package Waveform 2 Waveform 2 Waveform 1, 2 Waveform 2 Waveform 1 Waveform 1, 2 Test circuit and waveforms Waveform 4 2.5 3.0 1.0 1.5 3.0 4.0 4.0 5.0 5.5 3.0 4.5 2.0 TYP 4.0 5.0 3.0 3.0 5.0 5.5 6.0 6.5 7.5 5.0 7.5 6.5 2.0 2.0 1.0 Tamb = +25C SYMBOL PARAMETER TEST CONDITION VCC = +5.0V CL = 50pF, RL = 500 MIN tPLH tPHL tPLH tPHL Propagation delay An to IAMC (latches preset) Propagation delay IAREQ to IAMC Waveform 2 Waveform 2 10.5 7.0 6.5 2.5 TYP 14.5 12.0 8.0 4.5 MAX 18.0 15.0 11.0 7.0 2.0 MAX 7.0 7.5 5.5 5.5 8.0 8.5 8.5 9.5 10.0 8.0 10.0 9.5 MAX 8.0 7.5 12.0 13.5 8.0 9.0 1.0 B PORT LIMITS Tamb = 0C to +70C VCC = +5.0V 10% MIN 2.0 2.5 1.0 1.0 3.0 3.5 3.5 3.5 5.0 2.5 4.0 2.0 1.0 1.0 MAX 8.0 9.0 6.0 6.5 8.5 9.5 10.0 11.5 11.0 8.5 11.0 11.0 3.0 3.0 2.0 Tamb = 0C to +70C VCC = +5.0V 10% MIN 9.5 6.0 6.0 2.0 MAX 20.0 17.5 11.5 8.0 ns ns UNIT CL = 50pF, RL = 500 ns ns ns ns ns ns ns ns UNIT CD = 30pF, RU = 9 Tamb = 0C to +70C VCC = +5.0V 10% MIN 2.5 2.5 6.0 7.5 2.5 4.0 MAX 8.5 8.0 14.0 16.0 9.0 10.0 1.0 ns ns ns ns UNIT CL = 50pF, RL = 500
IAMC PORT LIMITS (74F8966 only)
December 19, 1990
9
Philips Semiconductors FAST Products
Product specification
9-Bit address/data Futurebus transceiver, ADT
74F8965/74F8966
AC SETUP REQUIREMENTS
LIMITS Tamb = +25C SYMBOL PARAMETER TEST CONDITION VCC = +5.0V CL = 50pF, RL = 500 MIN tsu(H) tsu(L) th(H) th(L) tw(L) Setup time, high or low An to LE Hold time, high or low An to LE LE pulse width, low Waveform 3 Waveform 3 Waveform 3 2.5 0.0 4.0 2.5 4.0 TYP MAX Tamb = 0C to +70C VCC = +5.0V 10% MIN 3.0 0.0 5.0 3.0 4.5 MAX ns ns ns UNIT CL = 50pF, RL = 500
AC WAVEFORMS
Bn, LS, LE, OEB1, IAREQ VM tPLH Bn, IAMC VM VM tPHL VM An, Bn. IAMC An, Bn, LS, LE, OEB0, IAREQ VM tPHL VM VM tPLH VM
Waveform 1. Propagation delay for data or output enable to output
An, Bn VM VM th(L) tsu(L) LE VM VM VM tsu(H) tw(L) VM VM
Waveform 2. Propagation delay for data or output enable to output
An, Bn VM tsk(o)
th(H)
An, Bn
VM
Waveform 3. Data setup and hold times and LE pulse width
Waveform 4. Output skew
OEA
VM tPZH
VM tPHZ VM 0V VOH -0.3V
OEA
VM tPZL
VM tPLZ VM VOL +0.3V
An
An
Waveform 5. 3-state output enable time to high level and output disable time from high level
Waveform 6. 3-state output enable time to low level and output disable time from low level
Notes to AC waveforms 1. For all waveforms, VM = 1.5V. 2. The shaded areas indicate when the input is permitted to change for predictable output performance.
December 19, 1990
10
Philips Semiconductors FAST Products
Product specification
9-Bit address/data Futurebus transceiver, ADT
74F8965/74F8966
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION TEST SWITCH tPLZ, tPZL closed All other open
VIN PULSE GENERATOR RT D.U.T. tTLH (tr ) CL RL POSITIVE PULSE 90% VM 10% tw tTHL (tf ) AMP (V) 90% VM 10% Low V 90% VCC 7.0V VOUT RL NEGATIVE PULSE VM 10% tTHL (tf ) tw VM 10% tTLH (tr ) Low V 90% AMP (V)
Test circuit for 3-state outputs on A port
VCC 7.0V
Input pulse definition
VIN PULSE GENERATOR RT D.U.T. VOUT RU
INPUT PULSE REQUIREMENTS family tTLH tw 74F amplitude Low V VM rep. rate A port B port 3.0V 3.0V 0.0V 1.0V 1.5V 1.5V 1MHz 1MHz 500ns 500ns 2.5ns 4.0ns
tTHL 2.5ns 4.0ns
CD
Test circuit for outputs on B port DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RU = Pull up resistor; see AC electrical characteristics for value. CD = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
December 19, 1990
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